Here is the advance program for the annual Electronics Design Process (EDPS) workshop, EDP-2001. The program and conference chairs feel they have put together an excellent workshop program and have a number of interested well-known design and EDA experts participating in the program. They expect the sessions which include measuring design processes, nanometer RTL-through-layout design closure, liquid libraries, analog design flow directions and needs, design flow benchmark testing, system and SOC design flows, front-end design planning and physical design forecasting, and fast tool integration, to be quite interesting. The emphasis of the workshop is especially on bringing all attendees into the discussion on each topic. The IEEE DATC EDPS conference will be covered by the EE-Times. ====================================================================== SUNDAY, APRIL 8 1900-2100 Registration and Reception ====================================================================== MONDAY, APRIL 9 0800-0830 CONTINENTAL BREAKFAST 0830-0845 WELCOME David Hathaway (IBM Microelectronics), General Chair Andrew B. Kahng (UCSD), Program Chair 0845-0930 KEYNOTE 1 "General Issues in ASIC Design: Business and Methodology", George Doerre (IBM Microelectronics) 0930-0945 BREAK 0945-1145 SESSION 1: DESIGN METHODOLOGY CAPTURE AND MANAGEMENT 0945-1015 "Status and Evolution of IP Symphony", David Dick (Fujitsu) 1015-1045 "Fast Integration of EDA Tools and Scripting Language", Pinhong Chen (UC Berkeley / TSMC North America) and Kurt Keutzer (UC Berkeley) 1045-1115 "The UEDK: A VLSI CAD/EDA Learning-by-Example Platform", Jose' A.D.F. Lima (U. do Minho, Portugal) 1115-1145 Moderated Discussion, Workshop Attendees 1145-1245 LUNCH 1245-1445 SESSION 2: TOOL AND METHODOLOGY MEASUREMENT 1245-1315 "Key Performance Indicators of Methodology Capability", Ron Collett (Numetrics) 1315-1345 "Optimizing Cycle Time Through the Use of Design Metrics", Bill Bell (TI) 1345-1430 PANEL: Design and CAD Metrics - "On High Level Estimators and Constructors", Majid Sarrafzadeh and Jason Cong (UCLA) - "A METRICS System for Design Process Optimization", Andrew B. Kahng (UCSD) and Stefanus Mantik (UCLA / Cadence) - "Tool Benchmarking: Status and Directions", Justin Harlow (SRC) 1430-1445 Moderated Discussion, Workshop Attendees 1445-1500 BREAK 1500-1730 SESSION 3: FRONT-END PLANNING AND PD METHODOLOGY 1500-1530 "A Eulogy for Wireload Models", Bill Bell (TI) 1530-1600 "Datamodels for Physical Synthesis: Some Practical Considerations for Library Support", Dwight Hill and Shir-Shen Chang (Synopsys) 1600-1630 "Design Planning Methodology for Rapid Chip Deployment", David E. Lackey (IBM Microelectronics) 1630-1700 "Open Design Rule Markup Language for STARC Open Design Rule Initiative", Takahide Inoue (UC Berkeley and JSIG VSIA), Hiroyuki Hara (STARC) and Tadahiko Nakamura (STARC) 1700-1730 Moderated Discussion, Workshop Attendees 1800-2100 DINNER Presentation and Discussion, Workshop Attendees "Design Processes Roadmap in the 2001 ITRS: Current Draft and Open Issues", Don Cottrell (SI2 and member, U.S. Design TWG for ITRS-2001) ====================================================================== TUESDAY, APRIL 10 0730-0815 CONTINENTAL BREAKFAST 0815-0945 SESSION 4: LIQUID LIBRARY AND PERFORMANCE OPTIMIZATION METHODOLOGIES 0815-0845 "Semicustom Design: Synergies Between Full Custom and ASIC Design Flows in High-Performance Processor Design", Greg Northrop (IBM Research) 0845-0915 "Power and Performance Optimization of Cell-Based Designs with Intelligent Transistor Sizing and Cell Creation", Etsuji Yoneno (Hitachi ULSI Systems) and Philippe Hurat (NTI/Cadabra) 0915-0945 Moderated Discussion, Workshop Attendees 0945-1000 BREAK 1000-1200 SESSION 5: NANOMETER AND RTL-DOWN CLOSURE 1000-1030 "RTL-Down Data Models and Convergence Methodology", Patrick Groeneveld (Magma) 1030-1100 "Data Modeling and Convergence Methodology in Integration Ensemble", Lou Scheffer (Cadence) 1100-1145 PANEL: Physical Design Methodology Best Practices - Salil Raje (Monterey) - Paul Rodman (Reshape) - Aurangzeb Khan (Simplex/Altius) 1145-1200 Moderated Discussion, Workshop Attendees 1200-1330 LUNCH AND KEYNOTE 2 "The IC Implementation Tool Set", Gary Smith (Dataquest) 1330-1530 SESSION 6: MODELING AND METHODOLOGY FOR SOC AND SYSTEM DESIGN 1330-1400 "SOC Verification Software - Test Operating System", Robert Devins (IBM Microelectronics) 1400-1430 "High-Level Design Modeling and Design Handoff", Rajesh Gupta (UC Irvine) 1430-1500 "Using Esterel Approach to Design Complex Systems", Gilles Pelissier (STMicroelectronics) and Lionel Blanc (Esterel Technologies) 1500-1530 Moderated Discussion, Workshop Attendees 1530-1545 BREAK 1545-1745 SESSION 7: PANEL ON ANALOG MIXED-SIGNAL DESIGN FLOWS 1545-1615 "A Formal Top-Down Design Process of Analog Mixed-Signal Circuits", Ken Kundert (Cadence) 1615-1645 "Analog and Analog/Mixed-Signal Design Flows for Highly Productive Multi-company SOC Analog Design and Release", Ron Gyurcsik (Tality) 1645-1715 "Trends in AMS Design Methodology, Gary Smith (Dataquest) 1715-1745 Moderated Discussion, Workshop Attendees 1745 Adjourn ============================================================